Iii-v semiconductor devices with selective oxidation

ABSTRACT

Embodiments of the present invention provide methods for fabricating a semiconductor device with selective oxidation. One method may include providing a semiconductor substrate including a stack of two semiconductor layers; depositing an insulating material on the semiconductor substrate; forming a set of fins; selectively oxidizing one of the semiconductor layers; forming a dummy gate structure and a set of spacers along the sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized semiconductor layer.

RELATED APPLICATIONS

This patent application is a continuation application of and claimsbenefit or priority to U.S. patent application Ser. No. 16/402,267,filed May 3, 2019, which is a continuation application of U.S. patentapplication Ser. No. 15/136,048, filed Apr. 22, 2016, now U.S. Pat. No.10,367,060, which is a divisional application of U.S. patent applicationSer. No. 14/547,181, filed Nov. 19, 2014, each of which is incorporatedby reference herein in its entirety for all purposes.

BACKGROUND OF THE INVENTION

The present invention relates generally to semiconductor devices, andmore particularly to the formation of III-V semiconductor devices withstarting layers which can be selectively oxidized.

The fabrication of semiconductor devices involves forming electroniccomponents in and on semiconductor substrates, such as silicon wafers.These electronic components may include one or more conductive layers,one or more insulation layers, and doped regions formed by implantingvarious dopants into portions of a semiconductor substrate to achievespecific electrical properties. Semiconductor devices includetransistors, resistors, capacitors, and the like, with intermediate andoverlying metallization patterns at varying levels, separated bydielectric materials, which interconnect the semiconductor devices toform integrated circuits.

To electrically isolate semiconductor devices from each other, variousisolation techniques, such as trench isolation structures, have beenused. Viewing the vertical direction as into the depth, or thickness, ofa given substrate and the horizontal direction as being parallel to atop surface of the substrate, a trench isolation structure is verticallyoriented to provide insulating separation between semiconductor devicesat different horizontal locations. Traditionally, a semiconductorsurface is etched to form separate device regions, and resultingtrenches in between the separate device regions are filled withdielectric material to form the trench isolation structures.

A semiconductor substrate may also employ semiconductor-on-insulatorsubstrate arrangements, such as silicon-on-insulator (SOI) substrates.In a semiconductor on insulator arrangement, a semiconductor layer canbe formed above an insulation layer which has been formed on thesemiconductor substrate. Devices can be formed in the top semiconductorlayer. The insulating layer provides isolation from the substrate,thereby decreasing capacitance effects for both devices and electricalconnections. The top semiconductor layer can be etched, as describedabove, to provide trench isolation between device regions.

Growing an epitaxial insulating layer on a semiconductor substrate isknown. Oxides such as strontium titanium oxides (e.g., SrTiO₃) andyttrium oxides (e.g., Y₂O₃) have been grown on silicon substrates. Morerecently, epitaxial structures with closer lattice-matching have beengrown, allowing for silicon substrate/epitaxial oxide/epitaxial siliconmulti-layer structures. Grown epitaxial oxides with closerlattice-matching properties include oxides of rare earth metals and rareearth metal alloys, such as cerium, yttrium, lanthanum, samarium,gadolinium, europium, and combinations thereof (e.g., cerium oxides(CeO₂) and lanthanum yttrium oxides (La_(x)Y_(1-x))₂O₃).

SUMMARY

According to one embodiment of the present invention, a method forfabricating a semiconductor device with selective oxidation is provided,the method comprising: providing a semiconductor substrate comprising astack of two crystalline semiconductor layers, wherein the stack of twocrystalline semiconductor layers are disposed on a top surface of thesemiconductor substrate; depositing an insulating material on thesemiconductor substrate; etching one or more recesses into theinsulating material to form a set of fins; selectively oxidizing one ofthe two crystalline semiconductor layers; forming a dummy gate structureand a set of spacers along sides of the dummy gate structure; forming asource drain region adjacent to the dummy gate structure; removing thedummy gate structure; and releasing the selectively oxidized crystallinesemiconductor layer.

According to another embodiment of the present invention, asemiconductor structure is provided, the semiconductor structurecomprising: a stack of two crystalline semiconductor layers grown on astarting semiconductor substrate, wherein the stack of two crystallinesemiconductor layers comprises a first layer and a second layer; aplurality of fins patterned in the starting semiconductor substrate; agate structure and a set of spacers, wherein a portion of the gatestructure and the set of spacers are disposed around the plurality offins; a source drain region formed adjacent to the gate structure; and ahigh-K dielectric material disposed around the gate structure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B depict a plan view and a cross-sectional view of astarting semiconductor substrate on which a III-V device with selectiveoxidation may be formed, in accordance with an embodiment of the presentinvention;

FIGS. 2A-C depict a plan view and cross-sectional views of an embodimentwhere device regions are created on the starting substrate of FIGS. 1Aand 1B through shallow trench isolation, in accordance with anembodiment of the present invention;

FIGS. 3A-C depict a plan view and cross-sectional views of the selectiveoxidation of one of the starting semiconductor substrate layers, inaccordance with an embodiment of the present invention;

FIGS. 4A-C depict a plan view and cross-sectional views of the formationof dummy gates in the device regions created in FIGS. 2A-C, inaccordance with an embodiment of the present invention;

FIGS. 5A-D depict a plan view and cross-sectional views of the formationof source and drain regions on either side of the dummy gates of FIGS.4A-C, in accordance with an embodiment of the present invention;

FIGS. 6A-D depict a plan view and cross-sectional views of thedeposition of an insulator layer over the device regions of FIGS. 2A-C,covering the source and drain regions of FIGS. 5A-D, and the subsequentplanarization of the insulator layer to expose the tops of the dummygates created in FIGS. 4A-C, in accordance with an embodiment of thepresent invention;

FIGS. 7A-D depict a plan view and cross-sectional views of the removalof the dummy gates created in FIGS. 4A-C, in accordance with anembodiment of the present invention;

FIGS. 8A-D depict a plan view and cross-sectional views of the releaseof the selectively oxidized layer created in FIGS. 3A-C, in accordancewith an embodiment of the present invention; and

FIGS. 9A-D depict a plan view and cross-sectional views of depositing ahigh-K dielectric and forming replacement gates between sets of sidewallspacers, in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION

The formation of nanowires on a Si substrate may be difficult whencrystalline semiconductors are stacked on an insulator. Embodiments ofthe present invention provide a fabrication process for a III-Vsemiconductor device with crystalline starting layers which aresubsequently selectively oxidized to become an insulator. Growing thestarting layer as a semiconductor layer is less effective than growing asingle crystal insulator starting layer. Detailed description ofembodiments of the claimed structures and methods are disclosed herein;however, it is to be understood that the disclosed embodiments aremerely illustrative of the claimed structures and methods that may beembodied in various forms. In addition, each of the examples given inconnection with the various embodiments is intended to be illustrative,and not restrictive. Further, the figures are not necessarily to scale,some features may be exaggerated to show details of particularcomponents. Therefore, specific structural and functional detailsdisclosed herein are not to be interpreted as limiting, but merely as arepresentative basis for teaching one skilled in the art to variouslyemploy the methods and structures of the present disclosure.

References in the specification to “one embodiment”, “an embodiment”,“an example embodiment”, etc., indicate that the embodiment describedmay include a particular feature, structure, or characteristic, butevery embodiment may not necessarily include the particular feature,structure, or characteristic. Moreover, such phrases are not necessarilyreferring to the same embodiment. Further, when a particular feature,structure, or characteristic is described in connection with anembodiment, it is submitted that it is within the knowledge of oneskilled in the art to affect such feature, structure, or characteristicin connection with other embodiments whether or not explicitlydescribed.

For purposes of the description hereinafter, the terms “upper”, “lower”,“right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, andderivatives thereof shall relate to the disclosed structures andmethods, as oriented in the drawing figures. The terms “on”, “over”,“overlying”, “atop”, “positioned on”, or “positioned atop” mean that afirst element, such as a first structure, is present on a secondelement, such as a second structure, wherein intervening elements, suchas an interface structure, may be present between the first element andthe second element. The terms “direct contact”, “directly on”, or“directly over” mean that a first element, such as a first structure,and a second element, such as a second structure, are connected withoutany intermediary conducting, insulating, or semiconductor layers at theinterface of the two elements. The terms “connected” or “coupled” meanthat one element is directly connected or coupled to another element, orintervening elements may be present. The terms “directly connected” or“directly coupled” mean that one element is connected or coupled toanother element without any intermediary elements present.

Referring now to the figures, FIG. 1A is a plan view of a startingsubstrate on which III-V devices with selective oxidation may be formed,and FIG. 1B is a cross-sectional view of FIG. 1A, taken along the line1B-1B. The starting substrate includes base layer(s) 102, and may becomposed of any crystalline material(s) known in the art. In thisexemplary embodiment, base layer(s) 102 includes a layer of Ge, which isapproximately from 100 nm to 1 micrometer in thickness, on top of aninsulator. A stack of two crystalline semiconductor layers, layer 104and layer 106 are grown on the top surface of base layer(s) 102. In thisexemplary embodiment, layer 104 is a single crystal semiconductormaterial composed of AlAs, and is approximately 10 nm in thickness. Inother embodiments, layer 104 may be composed of any semiconductormaterial capable of being oxidized to a mechanically stable insulator.Layer 106 is a single crystal semiconductor layer, and may be composedof InGaAs, GaAs, III-V materials, or any other semiconducting material.In this exemplary embodiment, layer 106 is composed of InGaAs and isapproximately 10 nm in thickness. As depicted in FIG. 1B, there are twostacks (i.e., grouping of one layer 104 and one layer 106) formed on thetop surface of base layer(s) 102. In other embodiments, more than twostacks or a single stack may be formed on the top surface of baselayer(s) 102.

Referring now to FIGS. 2A-C, FIG. 2A is a plan view of the processingstep of fin regions patterned on the starting substrate of FIGS. 1A and1B, FIG. 2B is a cross-sectional view of FIG. 2A, taken along the line2B-2B, and FIG. 2C is a cross-sectional view of FIG. 2A, taken along theline 2C-2C. The fins are formed using a standard etch process.Subsequent to the formation of the fins, device regions are createdthrough shallow trench isolation (STI) within the starting substrate. Ina preferred embodiment, the shallow trenches are filled with one or moreinsulating materials 108, such as SiO₂, to isolate the fins from eachother. This prevents electrical current leakage between adjacentsemiconductor device components, preventing one device region fromaffecting another or shorting out through contact with another.

Referring now to FIGS. 3A-3C, FIG. 3A is a plan view of the processingstep of selective oxidation of layer 104 of the starting substrate, FIG.3B is a cross-sectional view of FIG. 3A, taken along the line 3B-3B, andFIG. 3C is a cross-sectional view of FIG. 3A, taken along the line3C-3C. The starting substrate is exposed at a temperature between 350°C. to 550° C. in water vapor, to selectively oxidize layer 104 (AlAs inthis embodiment) to become oxidized layer 110. The composition of layer104 is initially chosen to be more readily oxidized than layer 106, andalso as a close lattice match to layer 106. Oxidized layer 110 acts asan insulating layer within the stacked crystalline structure. In thisexemplary embodiment, oxidized layer 110 is composed of Al₂O₃.

Referring now to FIGS. 4A-4C, FIG. 4A is a plan view of the processingstep of dummy gates 112 and sidewall spacers 113 in the fin regions onthe starting substrate, FIG. 4B is a cross-sectional view of FIG. 4A,taken along the line 4B-4B, and FIG. 4C is a cross-sectional view ofFIG. 4A, taken along the line 4C-4C. Dummy gates 112 (i.e., sacrificialgate structures) are formed and, after formation of source and drainregions 116 (depicted in FIGS. 5A-D), may be selectively etched andreplaced. One exemplary process for forming dummy gates 112 comprisesdepositing a dielectric layer over the starting substrate and apolysilicon layer over the dielectric layer. A lithography/gate etchprocess removes unnecessary portions of the stacked layers to leavedummy gates 112, comprised of a gate oxide (not pictured) andpolysilicon layer 114. Ultimately, dummy gates 112 may be comprised ofany material that can be etched selectively to the underlying uppersemiconductor layer. A set of sidewall spacers 113 are formed adjacentto dummy gates 112, i.e., in direct contact with the sidewall of dummygate 112. A sidewall spacer typically has a width ranging from 2 nm to15 nm, as measured from the sidewall of a gate structure. Sidewallspacers 113 may be composed of a dielectric, such as a nitride, oxide,oxynitride, or a combination thereof. In one embodiment, sidewallspacers 113 are composed of silicon nitride (Si₃N_(x)). Those skilled inthe art will recognize that a “set” of sidewall spacers 113 may actuallycomprise a single spacer formed around the entire gate.

Referring now to FIGS. 5A-D, FIG. 5A is a plan view of the processingstep of source and drain regions 116 formation, FIG. 5B is across-sectional view of FIG. 5A, taken along the line 5B-5B, FIG. 5C isa cross-sectional view of FIG. 5A, taken along the line 5C-5C, and FIG.5D is a cross-sectional view of FIG. 5A, taken along the line 5D-5D.Source and drain regions 116 formation includes a number ofhigh-temperature steps (e.g., implants and anneals). In this exemplaryembodiment, source and drain regions 116 are formed using epitaxy. Inanother embodiment, source and drain regions 116 are formed using an ionimplantation process.

Referring now to FIGS. 6A-6D, FIG. 6A is a plan view of the processingstep of depositing insulator 118, FIG. 6B is a cross-sectional view ofFIG. 6A, taken along the line 6B-6B, FIG. 6C is a cross-sectional viewof FIG. 6A, taken along the line 6C-6C, and FIG. 6D is a cross-sectionalview of FIG. 6A, taken along the line 6D-6D. Insulator 118 is planarizedusing a standard planarization method in the art, and may be depositedusing, for example, chemical vapor deposition (CVD). Variations of CVDprocesses may also be used, including, but not limited to, atmosphericpressure CVD (APCVD), low pressure CVD (LPCVD), and plasma enhanced CVD(PECVD). Other deposition techniques may also be used. Followingdeposition of insulator 118, insulator 118 is planarized until the uppersurfaces of dummy gates 112 are exposed. Planarization is a materialremoval process that employs at least mechanical forces, such asfrictional media, to produce a planar surface. In one embodiment, theplanarization process includes chemical mechanical polishing (CMP) orgrinding. CMP is a material removal process which uses both chemicalreactions and mechanical forces to remove material and planarize asurface. The preferred method for exposing polysilicon layer 114 isknown as poly open planarization (POP) chemical mechanical planarization(CMP), or poly open CMP.

Referring now to FIGS. 7A-7D, FIG. 7A is a plan view of the processingstep of the removal of dummy gates 112, FIG. 7B is a cross-sectionalview of FIG. 7A, taken along the line 7B-7B, FIG. 7C is across-sectional view of FIG. 7A, taken along the line 7C-7C, and FIG. 7Dis a cross-sectional view of FIG. 7A, taken along the line 7D-7D. Oncethe gate stack is exposed, dummy gates 112 are removed through aselective etch process, selective to the substrate/channel material andsidewall spacers 113. In this exemplary embodiment, a first etch removespolysilicon layer 114 and is selective to sidewall spacers 113. Theetchant may be an isotropic etch or an anisotropic etch. One example ofan isotropic etch is a wet chemical etch. The anisotropic etch mayinclude reactive-ion etching (RIE). Other examples of anisotropicetching that can be used during this process include ion beam etching,plasma etching, or laser ablation.

Referring now to FIGS. 8A-8D, FIG. 8A is a plan view of the processingstep of the release of layer 110 (Al₂O₃), FIG. 8B is a cross-sectionalview of FIG. 8A, taken along the line 8B-8B, FIG. 8C is across-sectional view of FIG. 8A, taken along the line 8C-8C, and FIG. 8Dis a cross-sectional view of FIG. 8A, taken along the line 8D-8D. Inthis exemplary embodiment, an etching process known in the art, use ofdilute HF, is used to etch layer 110, in order to release layer 110selective to sidewall spacers 113, channel layer 106, and dielectricinsulator 118.

Referring now to FIGS. 9A-D, FIG. 9A is a plan view of the processingstep of the deposition of high-K material 126 and formation ofreplacement gates 124, FIG. 9B is a cross-sectional view of FIG. 9A,taken along the line 9B-9B, FIG. 9C is a cross-sectional view of FIG.9A, taken along the line 9C-9C, and FIG. 9D is a cross-sectional view ofFIG. 9A, taken along the line 9D-9D. High-K material 126 may be composedof, for example, HfO, ZrO, or TiO. Replacement gates 124 are formedbetween the existing sidewall spacers 113, and may be composed of anymetal, for example, W or Cu. High-K material 126 is deposited around theformed replacement gates 124. Standard middle of the line and back endof the line (BEOL) processes known in the art may be performed tocomplete the semiconductor chip (not depicted).

Having described the preferred embodiments of a method for selectivelyoxidizing layers within a III-V semiconductor device (which are intendedto be illustrative and not limiting), it is noted that modifications andvariations may be made by persons skilled in the art in light of theabove teachings. It is, therefore, to be understood that changes may bemade in the particular embodiments disclosed which are within the scopeof the invention, as outlined by the appended claims.

In certain embodiments, the fabrication steps depicted above may beincluded on a semiconductor substrate consisting of many devices and oneor more wiring levels to form an integrated circuit chip. The resultingintegrated circuit chip(s) can be distributed by the fabricator in rawwafer form (that is, as a single wafer that has multiple unpackagedchips), as a bare die, or in a packaged form. In the latter case thechip is mounted in a single chip package (such as a plastic carrier,with leads that are affixed to a motherboard or other higher levelcarrier) or in a multichip package (such as a ceramic carrier that haseither or both surface interconnections or buried interconnections). Inany case, the chip is then integrated with other chips, discrete circuitelements, and/or other signal processing devices as part of either (a)an intermediate product, such as a motherboard, or (b) an end product.The end product can be any product that includes integrated circuitchips, ranging from toys and other low-end applications, to advancedcomputer products having a display, a keyboard or other input device,and a central processor.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

1. (canceled)
 2. A method of fabricating a semiconductor device, themethod comprising: providing a stack of two layers disposed on a baselayer, wherein a first layer of the two layers is an oxidized layer;forming a dummy gate; forming source and drain regions in contact withsides of the two layers; removing the dummy gate to provide a gateopening; etching the first layer through the gate opening to provide alower gate region; and forming a replacement gate between a plurality ofwalls, the replacement gate comprising an upper gate portion having afirst width and a lower gate portion having a second width, wherein thelower gate portion is located in the lower gate region below the uppergate portion, and wherein the second width is greater than the firstwidth.
 3. The method of claim 2, wherein providing the stack of twolayers disposed on the base layer comprises: depositing two crystallinesemiconductor layers on the base layer; and selectively oxidizing one ofthe two crystalline semiconductor layers to provide the first layer. 4.The method of claim 3, wherein selectively oxidizing the one of the twocrystalline semiconductor layers comprises: exposing the semiconductorsubstrate in water vapor at a temperature in a range of approximately350 degrees to approximately 550 degrees Celsius.
 5. The method of claim3, wherein the two crystalline semiconductor layers comprise asemiconducting material selected from a group consisting of indiumgallium arsenide (InGaAs) and gallium arsenide (GaAs).
 6. The method ofclaim 3, further comprising: performing shallow trench isolation withinthe base layer to form a plurality of trenches exposing the first layerand a second layer; and depositing an insulator into the plurality oftrenches.
 7. The method of claim 2, further comprising: depositing ahigh-K insulator around at least part of the replacement gate.
 8. Themethod of claim 2, wherein the base layer comprises germanium (Ge). 9.The method of claim 8, wherein the Ge has a thickness in a range ofapproximately 100 nanometers to approximately 1 micrometer.
 10. A methodof fabricating a semiconductor device, the method comprising: disposinga stack of two crystalline semiconductor layers on a base layer;selectively oxidizing a first of the two crystalline semiconductorlayers to provide a first layer; removing a dummy gate structure toprovide a gate opening; etching the first layer through the gate openingto provide a lower gate region; and forming a replacement gate between aplurality of walls, the replacement gate comprising an upper gateportion having a first width and a lower gate portion having a secondwidth, wherein the lower gate portion is located in the lower gateregion, and wherein the second width is greater than the first width.11. The method of claim 10, further comprising: forming source and drainregions in contact with the first layer and a second layer of the twocrystalline semiconductor layers.
 12. The method of claim 10, whereinselectively oxidizing the first of the two crystalline semiconductorlayers comprises: exposing the semiconductor substrate in water vapor ata temperature in range of approximately 350 degrees to approximately 550degrees Celsius.
 13. The method of claim 10, wherein the stack of twocrystalline semiconductor layers comprises a semiconducting materialselected from a group consisting of indium gallium arsenide (InGaAs) andgallium arsenide (GaAs).
 14. The method of claim 10, further comprising:performing shallow trench isolation within the base layer to form aplurality of trenches exposing the first layer and a second layer of thetwo crystalline semiconductor layers; and depositing an insulator intothe plurality of trenches of the base layer.
 15. The method of claim 10,further comprising: depositing a high-K insulator around at least partof the replacement gate.
 16. The method of claim 10, wherein the baselayer comprises germanium (Ge).
 17. The method of claim 16, wherein theGe has a thickness in a range of approximately 100 nanometers toapproximately 1 micrometer.
 18. A method of fabricating a semiconductordevice, the method comprising: providing a stack of two layers disposedon a base layer, wherein a first layer of the two layers is an oxidizedlayer; forming source and drain regions in contact with sides of the twolayers; removing a dummy gate to provide a gate opening; etching thefirst layer through the gate opening to provide a lower gate region; andforming a replacement gate between a plurality of walls, the replacementgate comprising an upper gate portion having a first width and a lowergate portion having a second width, wherein the lower gate portion islocated in the lower gate region, and wherein the second width isgreater than the first width.
 19. The method of claim 18, whereinproviding the stack of two layers disposed on the base layer comprises:depositing two crystalline semiconductor layers on the base layer; andselectively oxidizing one of the two crystalline semiconductor layers toprovide the first layer.
 20. The method of claim 19, further comprising:performing shallow trench isolation within the base layer to form aplurality of trenches exposing the first layer and a second layer of thetwo crystalline semiconductor layers; and depositing an insulator intothe plurality of trenches of the base layer.
 21. The method of claim 20,further comprising: depositing a high-K insulator around at least partof the replacement gate.